EDN

Reuse UVM RTL verification tests for gate level simulation

When we verify a System on Chip (SoC) that embeds microprocessors with several digital peripherals, and possibly analog blocks as well, we want to check all the implemented features and possible ...
Semiconductor Engineering

UVM: What’s Stopping You?

These days, verification of the most complex designs is performed using a standard verification methodology, probably SystemVerilog-based UVM. Many verification teams have ramped up on UVM, but others ...
Electronic Design

Make the Move from Module-Based Mixed-Signal Verification to UVM

This file type includes high resolution graphics and schematics when applicable. This article discusses techniques used to achieve this transition, including proxy SystemVerilog interface task calls ...
TechRepublic

Reusability of Test Bench of UVM for Bidirectional Router and AXI Bus

The predictive analysis of the design to ensure that, it will perform the given I/O function is performed through functional verification. Verification has become the dominant cost in any of the ...
EDN

UVCs save time in SoC verification

Despite various methodologies that have developed in recent years and optimization methods used in EDA tools to simulate large and complex designs, verification engineers frequently complain of ...
EDN

A SystemC-based UVM verification infrastructure

My company, TVS, recently completed a SystemC-based Universal Verification Methodology (UVM) project for Blu Wireless Technology, a UK-based company that develops silicon-proven mmWave wireless ...